View ADP1828LC-EVALZ_604408.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Synchronous Buck PWM, Step-Down, DC-to-DC Controller ADP1828
FEATURES
Wide bias voltage range 3.0 V to 18 V Wide power stage input range 1 V to 24 V Wide output voltage range: 0.6 V to 85% of input voltage 0.85% accuracy at 0oC to 70oC All N-channel MOSFET design for low cost Fixed-frequency operation at 300 kHz, 600 kHz, or resistor adjustable 300 kHz to 600 kHz Clock output for synchronizing other controllers No current sense resistor required Internal linear regulator Voltage tracking for sequencing Soft start and thermal overload protection Overvoltage and undervoltage power-good indicator 15 A shutdown supply current Available in a 20-lead QSOP
to regulate an output voltage as low as 0.6 V to 85% of the input voltage and is sized to handle large MOSFETs for point-of-load regulators. The ADP1828 is ideal for a wide range of high power applications, such as DSP and processor core I/O power, and general-purpose power in telecommunications, medical imaging, PC, gaming, and industrial applications. It operates from input bias voltages of 3 V to 18 V with an internal LDO that generates a 5 V output for input bias voltages greater than 5.5 V. The ADP1828 operates at a pin-selectable, fixed switching frequency of either 300 kHz or 600 kHz, or at any frequency between 300 kHz and 600 kHz with a resistor. The switching frequency can also be synchronized to an external clock up to 2x the part's nominal oscillator frequency. The clock output can be used for synchronizing additional ADP1828s (or the ADP1829 controllers), thus eliminating the need for an external clock source. The ADP1828 includes soft start protection to limit any inrush current from the input supply during startup, reverse current protection during soft start for a precharged output, as well as a unique adjustable lossless current-limit scheme utilizing external MOSFET RDSON sensing. For applications requiring power-supply sequencing, the ADP1828 provides a tracking input that allows the output voltage to track during startup, shutdown, and faults. The additional supervisory and control features include thermal overload, undervoltage lockout, and power good. The ADP1828 operates over the -40C to +125C junction temperature range and is available in a 20-lead QSOP.
VIN = 10V TO 18V CIN 180F x2 20V D1 C4 0.47F RCL 1.8k
APPLICATIONS
Telecom and networking systems Base station power Set-top boxes, game consoles Printers and copiers Medical imaging systems DSP and microprocessor core power supplies DDR termination
GENERAL DESCRIPTION
The ADP1828 is a versatile and synchronous PWM voltage mode buck controller. It drives an all N-channel power stage
C5 1F VREG IN R6 100k C6 1F EN FREQ SYNC PGOOD COMP C2 33pF R8 20k C3 5.6nF CSS 200nF SS PV
C7 1F TRK BST DH SW CSL DL PGND FB CLKOUT CLKSET GND AGND
ADP1828
M1 L1 = 0.82H M2 x2 COUT2 1000F x2
OUTPUT 1.8V, 20A COUT1 R3 47F 7.5k X5R C1 6.3V R1 20k 680pF R2 10k
AGND PGND
fSW = 300kHz CIN: SANYO, OSCON 20SP180M COUT2: SANYO, POSCAP 2R5TPD1000M5 L1: WURTH ELEKTRONIC, 0.82H, 744355182
Figure 1. Typical Application Circuit with 20 A Output
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
06865-001
D1: BAT54 M1: INFINEON, BSC080N03LS M2: INFINEON, 2 x BSC030N03LS
ADP1828 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Simplified Block Diagram ............................................................... 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 14 Input Power ................................................................................. 14 Internal Linear Regulator .......................................................... 14 Soft Start ...................................................................................... 14 Error Amplifier ........................................................................... 15 Current-Limit Scheme ............................................................... 15 MOSFET Drivers ........................................................................ 15 Setting the Output Voltage ........................................................ 16 Switching Frequency Control and Synchronization .............. 16 Compensation ............................................................................. 17 Power-Good Indicator ............................................................... 17 Thermal Shutdown..................................................................... 17 Shutdown Control ...................................................................... 17 Tracking ....................................................................................... 17 Application Information ................................................................ 18 Selecting the Input Capacitor ................................................... 18 Output LC Filter ......................................................................... 18 Selecting the MOSFETs ............................................................. 19 Setting the Current Limit .......................................................... 20 Accurate Current-Limit Sensing .............................................. 20 Feedback Voltage Divider ......................................................... 20 Compensating the Voltage Mode Buck Regulator ................. 20 Soft Start ...................................................................................... 24 Switching Noise and Overshoot Reduction ............................ 24 Voltage Tracking ......................................................................... 24 Coincident Tracking .................................................................. 25 Ratiometric Tracking ................................................................. 25 Thermal Considerations............................................................ 27 PCB Layout Guideline ................................................................... 28 Recommended Component Manufacturers ........................... 29 Application Circuits ....................................................................... 30 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
9/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADP1828 SPECIFICATIONS
IN = 12 V, PV = VEN = VTRK = 5 V, SYNC = GND, unless otherwise specified. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). TJ = -40C to +125C, unless otherwise specified. Typical values are at TA = 25C. Table 1.
Parameter POWER SUPPLY IN Input Voltage IN Input Voltage IN Quiescent Current IN Shutdown Current VREG-to-GND Shutdown Impedance VREG Undervoltage Lockout Threshold VREG Undervoltage Lockout Hysteresis ERROR AMPLIFER FB Regulation Voltage Conditions PV is tied to VREG, IN is not tied to VREG (using internal regulator) IN = PV = VREG, IN is tied to VREG (not using internal regulator) Not switching, IVREG = 0 mA EN = GND EN = GND, IN is not tied to VREG VREG rising VREG falling TA = 25C, TRK > 700 mV TA = 0C to +70C, TRK > 700 mV TJ = -40C to +125C, TRK > 700 mV Min 5.5 3.0 1.5 5 1.6 2.7 0.125 600 Typ Max 18 5.5 3.0 15 3.0 Unit V V mA A M V V mV mV mV nA dB MHz A A V V V V mV mV mA mA V F V % ns ns k k mV V 600 +5 100 mV mV nA
2.4
597 595 591
FB Input Bias Current Open-Loop Voltage Gain Gain-Bandwidth Product COMP Sink Current COMP Source Current COMP Clamp High Voltage COMP Clamp Low Voltage LINEAR REGULATOR VREG Output Voltage VREG Load Regulation VREG Line Regulation VREG Current Limit VREG Short-Circuit Current IN to VREG Dropout Voltage 1 VREG Minimum Output Capacitance PWM CONTROLLER VRAMP Peak-to-Peak Voltage 2 DH Maximum Duty Cycle DH Minimum On Time DL Minimum On Time SOFT START SS Pull-Up Resistance SS Pull-Down Resistance SS to FB Offset Voltage SS Pull-Up Voltage TRACKING TRK Common-Mode Input Voltage Range TRK to FB Offset Voltage TRK Input Bias Current
IN = VREG = 3V IN = 12 V
5 70 20 600 120 2.4 3.6 0.75 4.75 5.0 -10 1 220 140 0.6
603 605 609 100
IN = 5 V+ dropout voltage to 18 V, IVREG =100 mA TJ = -40C to +125C IVREG = 0 mA to 100 mA, IN = 5.25 V to 18 V IN = 5 V+ dropout voltage to 18 V, no load VREG drops to 4 V VREG drops to 0.4 V IVREG = 100 mA, IN < 5 V
5.25
60 1 0.7 91
200 1.0
FREQ = GND (300 kHz) Any frequency Any frequency SS = GND SS = 0.6 V SS = 0 mV to 500 mV
1.0 93 100 200 90 6 -45 0.8
1.45
TRK = 0 mV to 500 mV
0 -5.5
Rev. 0 | Page 3 of 32
ADP1828
Parameter OSCILLATOR Oscillator Frequency Conditions SYNC = FREQ = GND SYNC = GND, FREQ = VREG RFREQ = 57.6 k RFREQ = 35.7 k RFREQ = 24.9 k FREQ = GND FREQ = VREG Min 240 480 240 370 480 300 600 200 Typ 300 600 300 450 600 Max 360 720 360 530 720 600 1200 Unit kHz kHz kHz kHz kHz kHz kHz ns pF mV A ns ns ns ns ns ns ns ns ns ns V V V A V V A k C C
SYNC Synchronization Range SYNC Input Pulse Width SYNC Pin Capacitance CURRENT SENSE CSL Threshold Voltage CSL Output Current Current Sense Blanking Period GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall Time DH or DL Driver RON, Sourcing Current 3, 4 DH or DL Driver RON, Sinking Current3, 4 DH or DL Driver RON, Sourcing Current DH or DL Driver RON, Sinking Current DH to DL, DL to DH Dead Time CLOCK OUT CLOCKOUT Pulse Width CLKOUT Rise or Fall Time SYNC to CLKOUT Propagation Delay, tPD SYNC to CLKOUT Propagation Delay, tPD LOGIC THRESHOLDS SYNC, CLKSET, FREQ Logic High SYNC, CLKSET Logic Low FREQ Logic Low CLKSET, SYNC, FREQ Input Leakage Current EN Input Threshold EN Input Threshold Hysteresis EN Current Source EN Input Impedance to 5 V Zener THERMAL SHUTDOWN Thermal Shutdown Threshold 4 Thermal Shutdown Hysteresis4
5 Relative to PGND CSL = PGND -17 42 -38 50 100 15 10 15 10 2 1.5 2.3 2 40 360 10 40 52 1.8 0.4 0.25 1 1.1 EN = 0 V to 3.0 V EN = 5.5 V to 18 V -0.1 1.5 0.2 -0.6 100 145 15 1.8 -1.5 -58 56
CDH = 3 nF, VBST - VSW = 5 V CDH = 3 nF, VBST - VSW = 5 V CDL = 3 nF CDL = 3 nF Sourcing 1.5 A with a 0.1 s pulse Sinking 1.5 A with a 0.1 s pulse IN = VREG = 3 V; sourcing 1 A with a 0.1 s pulse IN = VREG = 3 V; sinking 1 A with a 0.1 s pulse
CCLKOUT = 47 pF CCLKOUT = 47 pF, CSYNC = 5 pF CCLKOUT = 47 pF, CSYNC = 5 pF, IN < 5 V
CLKSET, SYNC, FREQ = 0 V or VREG
Rev. 0 | Page 4 of 32
ADP1828
Parameter POWER GOOD FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis PGOOD Propagation Delay PGOOD Off Leakage Current PGOOD Output Low Voltage
1
Conditions VFB rising VFB falling
Min 700 500
Typ 750 50 550 50 8 150
Max 810 585
Unit mV mV mV mV s A mV
VPGOOD = 5.5 V IPGOOD = 10 mA
1 500
Connect IN to VREG when IN < 5.5 V. For applications with IN < 5.5V and IN not connected to VREG, keep in mind that VREG = VIN - dropout. VREG needs to be 3 V for proper operation. VRAMP = 1.0 V x fOSC/fSW, where fOSC is the natural oscillator frequency and fSW is the actual switching frequency. If SYNC is not used, then fOSC = fSW. If SYNC is used, then fSW = fSYNC. 3 With a 5 V drive, the peak source or sink current could be up to 2.5 A and 3.3 A, respectively, when driving external power MOSFETs. The duration of the peak current pulse is generally in the order of 10 ns. 4 Guaranteed by design and characterization. Not subject to production test.
2
Rev. 0 | Page 5 of 32
ADP1828 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter IN, TRK EN PV, SYNC, FREQ, COMP, SS, FB, PGOOD, CLKSET, CLKOUT, VREG BST-to-GND, SW-to-GND BST-to-SW BST-to-GND, SW-to-GND, 50 ns transients SW-to-GND, 30 ns negative transients CSL-to-GND DH-to-GND DL-to-PGND PGND-to-GND JA, 20-Lead QSOP on a Multilayer PCB (Natural Convection)1 Operating Junction Temperature2 Storage Temperature Maximum Soldering Lead Temperature
1
Rating -0.3 V to +20 V -0.3 V < IN + 0.3 V -0.3 V to +6 V -0.3 V to +30 V -0.3 V to +6 V +38 V -7 V -1 V to +30 V (SW - 0.3 V) to (BST + 0.3 V) -0.3 V to (PV + 0.3 V) 2 V 83C/W -40C to +125C -65C to +150C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified all other voltages are referenced to GND.
ESD CAUTION
Junction-to-ambient thermal resistance (JA) of the package was calculated or simulated on a multilayer PCB. 2 The ADP1828 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature, TJ, of the device is dependent on the ambient temperature, TA, the power dissipation of the device, PD, and the junction to ambient thermal resistance of the package, JA. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula TJ = TA + PD x JA.
Rev. 0 | Page 6 of 32
ADP1828 SIMPLIFIED BLOCK DIAGRAM
IN
ADP1828
VREG 0.6V 0.8V REF 0.75V 0.55V UVLO IN THERMAL SHUTDOWN LINEAR REG
EN
100k
LOGIC BST
CLKOUT CLKSET
CLKOUT DRIVER
FAULT S Q PWM
DH
SW PV DL
FREQ OSCILLATOR SYNC RAMP
CLK PWM COMPARATOR VREG
R
Q
ILIM COMP FB TRK 0.6V ERROR AMPLIFIER 0.8V 0.55V FAULT 0.75V 50A
PGND
CSL
PGOOD
SS 6k
90k
Figure 2. Simplified Block Diagram
Rev. 0 | Page 7 of 32
06865-003
GND
ADP1828 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FREQ SYNC EN IN VREG GND COMP FB TRK
1 2 3 4 5 6 7 8 9 20 19 18
CLKOUT CLKSET BST DH SW CSL PGND DL
06865-004
ADP1828
TOP VIEW (Not to Scale)
17 16 15 14 13 12 11
PV PGOOD
SS 10
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 Mnemonic FREQ SYNC Description Frequency Control Input. Low for 300 kHz, high for 600 kHz, or connect a resistor from FREQ to GND to set the freerunning frequency between 300 kHz and 600 kHz. Frequency Synchronization Input. Accepts external signals between 300 kHz and 600 kHz if FREQ is set to low, or between 600 kHz and 1.2 MHz if FREQ is set to high. If fOSC is set by RFREQ, then the synchronization frequency range is from fOSC up to 600 kHz. If SYNC is not used, connect SYNC to GND or VREG. VSYNC can be driven up to 6 V even when VIN is less than 6 V. Enable Input. Drive EN high or tristate EN to turn on the ADP1828 controller, and drive it low to turn off. Connect EN to IN for automatic startup. Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 18 V to power the ADP1828 from LDO, VREG; tie PV to VREG. For input voltages between 3 V and 5.5 V, tie IN, PV, and VREG together. Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG. Bypass VREG to AGND plane with 1 F ceramic capacitor for stable operation, for example, a 10 V X5R 1 F ceramic capacitor is sufficient. The VREG output is 5 V when IN = 5 V + dropout. Connect IN to VREG and PV when IN = 3 V to 5.5 V. For applications with IN < 5.5 V and IN not connected to VREG, keep in mind that VREG = VIN - dropout. VREG needs to be 3 V for proper operation. Ground for Internal Circuits. Tie the bottom of the feedback dividers to this GND. Error Amplifier Output. Connect an RC network from COMP to FB for loop compensation. Voltage Feedback. Connect a resistor divider from the buck regulator output to GND and tie the tap to FB to set the output voltage. Tracking Input. To track a master voltage, drive TRK from a voltage divider from the master voltage. If the tracking function is not used, connect TRK to VREG. Soft Start Control Input. Connect a capacitor from SS to GND to set the soft start period. Open-Drain Power-Good Output. Sinks current when FB is out of regulation. Connect a pull-up resistor from PGOOD to VREG. Positive Input Voltage for Gate Driver DL. When IN is 3 V to 5.5 V, connect IN to VREG and PV. Connect a 1 F bypass capacitor from PV to PGND. When IN = 5.5 V to 18 V, connect PV to VREG. Low-Side (Synchronous Rectifier) Gate Driver Output. Power GND. Ground for gate driver. Current Sense Comparator Inverting Input. Connect a resistor between CSL and SW to set the current-limit offset. Switch Node Connection. High-Side (Switch) Gate Driver Output. Boost Capacitor Input. Powers the high-side gate driver DH. Connect a 0.22 F to 0.47 F ceramic capacitor from BST to SW and a Schottky diode from PV to BST. Clock Set Input. Setting CLKSET to Logic high (connect CLKSET to VREG) sets the CLKOUT to 2x the internal oscillator frequency and is in phase with the oscillator. Setting CLKSET to Logic low sets the CLKOUT to 1x the oscillator frequency and 180 out of phase. Clock Output. The CLKOUT frequency, fCLKOUT, is either 1x or 2x the oscillator frequency. CLKOUT can be used to synchronize another ADP1828 or ADP1829 controllers. Set fCLKOUT to 1x when synchronizing another ADP1828, or to 2x when synchronizing the ADP1829. If SYNC is used, fSYNC = fCLKOUT independent of the CLKSET voltage. CLKOUT is able to drive a 100 pF load.
Rev. 0 | Page 8 of 32
3 4 5
EN IN VREG
6 7 8 9 10 11 12 13 14 15 16 17 18 19
GND COMP FB TRK SS PGOOD PV DL PGND CSL SW DH BST CLKSET
20
CLKOUT
ADP1828 TYPICAL PERFORMANCE CHARACTERISTICS
95
90
300kHz 600kHz VIN = 12V VOUT = 1.8V TA = 25C
90 85
80
EFFICIENCY (%)
70
EFFICIENCY (%)
80 75 70 65 60
fSW = 600kHz VIN = 12V VOUT = 3.3V TA = 25C
60
50
40
55
06865-002
0
2
4
6
8
10 12 LOAD (A)
14
16
18
20
0
1
2 LOAD (A)
3
4
5
Figure 4. Efficiency vs. Load Current of Figure 1
Figure 7. Efficiency vs. Load Current of Figure 54
95 90 85
EFFICIENCY (%)
95 90 85
80 75 70 65 60
06865-005
EFFICIENCY (%)
VIN = 12V VIN = 15V
VIN = 3.3V
VIN = 5.5V
80 75 70 65 60 55 50
fSW = 300kHz
VOUT = 1.8V TA = 25C
fSW = 300kHz VIN = 12V VOUT = 1.8V TA = 25C
0
5
10 LOAD (A)
15
20
25
45
0
5
10
15 LOAD (A)
20
25
30
Figure 5. Efficiency vs. Load Current of Figure 1
Figure 8. Efficiency vs. Load Current of Figure 56
95 90
5.5 TA = 25C 5.0
85 80 75 70 65 60
06865-006
VREG OUTPUT (V)
EFFICIENCY (%)
fSW = 600kHz VIN = 3.3V VOUT = 1.2V TA = 25C
4.5
4.0
3.5
0
1
2 LOAD (A)
3
4
5
3.5
4.0 VIN (V)
4.5
5.0
5.5
Figure 6. Efficiency vs. Load Current of Figure 53
Figure 9. VREG in Dropout, No Load
Rev. 0 | Page 9 of 32
06865-009
55
3.0 3.0
06865-008
55
06865-007
30
50
ADP1828
5.000 4.995 4.990 VIN = 5.5V TA = 25C
3.0 2.5 600kHz TA = 25C
VREG OUTPUT (V)
4.985
300kHz 2.0
fOSC (%)
06865-010
4.980 4.975 4.970 4.965 4.960 4.955 0 20 40 60 VREG LOAD CURRENT (mA) 80 100
1.5
1.0
0.5
3
5
7
9
11 VIN (V)
13
15
17
Figure 10. VREG vs. Load Current
Figure 13. fOSC vs. VIN, Referenced at VIN = 3 V
5.000 4.995 4.990 4.985 NO LOAD VIN = 7V
T
VIN = 5.5V LOAD = 5A SW
VREG (V)
4.980 4.975 10mA LOAD 4.970 4.965 4.960 4.955
06865-011
1
2
100mA LOAD
VREG (AC-COUPLED)
-25
0
25 50 75 TEMPERATURE (C)
100
125
CH1 5.00V
BW
CH2 100mV
BW
M 400ns
A CH1
3.60V
Figure 11. VREG Voltage vs. Temperature
Figure 14. VREG Output of Figure 54
0.6025
5
VIN = 5.5V TA = 25C
FEEDBACK VOLTAGE (V)
0.6020 0.6015 0.6010 0.6005 0.6000 0.5995
06865-012
4
VREG OUTPUT (V)
3
2
1
0
50
100 150 VREG LOAD CURRENT (mA)
200
250
-15
10
35 60 TEMPERATURE (C)
85
110
135
Figure 12. VREG Current-Limit Foldback
Figure 15. Feedback Voltage vs. Temperature, VIN = 12 V
Rev. 0 | Page 10 of 32
06865-015
0
0.5990 -40
06865-014
4.950 -50
06865-013
4.950
0
ADP1828
2.0 1.5 1.0 0.5 VIN = 3V TO 18V fOSC = 300kHz OR 600kHz REFERENCE POINT IS AT 25C
1
T VOUT (AC-COUPLED)
fOSC (kHz)
STEP LOAD (5A TO 20A)
0 -0.5 -1.0 -1.5
06865-016
-25
0
25 50 75 TEMPERATURE (C)
100
125
150
CH1 100mV
BW
M 200s CH4 5.00A
A CH4
8.20A
Figure 16. fOSC vs. Temperature
6 TA = 25C 5
Figure 19. Load Transient Response of Figure 1, 5 A to 20 A, VIN = 12 V
T SW
QUIESCENT CURRENT (mA)
4
1
3
2
INPUT RIPPLE
2
1
3
OUTPUT RIPPLE
06865-020
2
5
8
11 VIN (V)
14
17
20
06865-017
0
CH2 50.0mV CH1 10.0V CH3 10.0mV BW
BW
M 1.00s
A CH1
5.80V
Figure 17. Supply Current vs. Input Voltage
Figure 20. Input and Output Ripple of Figure 54, 4 A Load
T SW
1
T
INPUT VOLTAGE (AC-COUPLED)
2
INPUT RIPPLE
2
OUTPUT (AC-COUPLED)
3
OUTPUT RIPPLE
3
4
STEP LOAD (1A TO 5A)
06865-018
CH1 10.0V CH3 50.0mV
BW
CH2 5.00V
BW
BW
M 1.00s
A CH1
6.40V
CH3 100mV
BW
CH2 200mV CH4 5.00A
BW
M 200s
A CH4
4.20A
Figure 18. Input and Output Ripple of Figure 1, 22 A Load
Figure 21. Load Transient Response of Figure 54, 1 A to 5 A, VIN = 12 V
Rev. 0 | Page 11 of 32
06865-021
06865-019
-2.0 -50
4
ADP1828
T VIN = 5V TO 9V TO 5V
1
T VIN
SS
2
VOUT
3
SW
1
VOUT (AC-COUPLED)
4
3
06865-022
CH1 2.00V CH3 50.0mV
BW
M 4.00ms
A CH1
6.08V
CH1 5.00V CH3 1.00V
BW
CH2 500mV CH4 5.00V
BW
M 2.00ms
A CH1
4.10V
Figure 22. Line Transient Response of Figure 1, No Load
Figure 25. Power-On Response, EN Tied to VIN
SHORT CIRCUIT APPLIED SHORT CIRCUIT REMOVED
1
T
SS
2
TRK
VOUT
3
FB VIN = 5.5V
INPUT CURRENT
4 1
06865-026 06865-027
06865-023
CH1 5.00V CH3 1.00V
BW
CH2 500mV CH4 5.00A
BW
M 20.0ms
A CH3
1.34V
CH1 200mV
BW
CH2 200mV
BW
M 20.0ms
A CH1
680mV
Figure 23. Output Short-Circuit Response
Figure 26. Tracking, TRK from 0 V to 1 V
T T EN
1
TRK AND FB SUPERIMPOSED VOUT
2
3
SS
1
CH1 5.00V CH3 1.00V
CH2 1.00V
BW
BW
M 4.00ms
A CH1
3.000V
06865-024
CH1 100mV
BW
CH2 100mV
BW
M 20.0ms
A CH1
352mV
Figure 24. Soft Start and Inrush Current of Figure 1
Figure 27. Tracking, TRK from 0 V to 0.5 V
Rev. 0 | Page 12 of 32
06865-025
ADP1828
T
T DH
1
DH
2
FB DL
3 2
SS CLKOUT
VIN = 0V TO 3V
4 4
VREG
06865-029
CH3 5.00V
CH2 10.0V CH4 5.00V
M 1.00s
A CH2
4.80V
CH1 5.00V CH3 200mV
BW BW
CH2 200mV CH4 2.00V
BW BW
M 4.00ms
A CH4
1.12V
Figure 28. CLKOUT, CLKSET = 0 V
Figure 31. Start into Precharged Output
T
T EN
1
DH
2
DL
3 2
DH
DL
4
CLKOUT
06865-030
3
06865-033
CH3 5.00V
CH2 10.0V CH4 5.00V
M 1.00s
A CH2
4.80V
CH1 5.00V CH3 5.00V
BW BW
CH2 10.0V
BW
M 4.00s
A CH2
8.20V
Figure 29. CLKOUT, CLKSET = 5 V
Figure 32. EN, Shutdown
T SYNC
1
DH
2
DL
3
CLKOUT
4
CH1 5.00V CH3 5.00V
CH2 10.0V CH4 5.00V
M 1.00s
A CH1
3.50V
Figure 30. SYNC
06865-031
Rev. 0 | Page 13 of 32
06865-032
ADP1828 THEORY OF OPERATION
The ADP1828 is a versatile, synchronous-rectified, fixedfrequency, pulse-width modulation (PWM), voltage mode, step-down controller capable of generating an output voltage as low as 0.6 V to 85% of the input voltage. It is ideal for a wide range of applications, such as DSP and processor core I/O supplies, general-purpose power in telecom, medical imaging, gaming, PCs, set-top boxes, and industrial controls. The ADP1828 controller operates directly from 3 V to 18 V. It includes fully integrated MOSFET gate drivers and a linear regulator for internal and gate drive bias. The ADP1828 operates at a pin-selectable, fixed switching frequency of either 300 kHz or 600 kHz, or operates at any frequency between 300 kHz and 600 kHz by connecting a resistor between FREQ and GND. The switching frequency can also be synchronized to an external clock up to 2x the part's nominal oscillator frequency. The built-in clock output can be used for synchronizing the ADP1829 and other ADP1828 controllers, thus eliminating the need for an external clock source. The ADP1828 also includes clockout, voltage tracking, thermal overload protection, undervoltage lockout, power good, soft start to limit inrush current from the input supply during startup, reverse current protection during soft start for precharged outputs, and an adjustable lossless current-limit scheme utilizing external MOSFET RDSON sensing. The ADP1828 operates over the -40C to +125C junction temperature range and is available in a 20-lead QSOP. For a supply voltage between 5.5 V and 18 V, connect IN to the supply voltage, and tie VREG to PV. For a supply voltage between 3 V and 5.5 V, connect IN, PV, and VREG to the supply voltage. In this case, the input supply voltage directly powers the lowside gate driver. While IN is limited to 18 V, the switching stage can run from up to 24 V and the BST pin can go to 30 V to support the gate drive. This can provide an advantage, for example, in the case of high frequency operation from high input voltage. Power dissipation in the ADP1828 can be limited by running IN from a low voltage rail while operating the switches from the high voltage rail.
INTERNAL LINEAR REGULATOR
The internal linear regulator has low dropout, meaning it can regulate its output voltage (VREG) close to the input voltage. It powers up the internal control circuitry and provides bias for the gate drivers when VREG is tied to PV. It is guaranteed to have more than 100 mA of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold MOSFETs driven at up to 1.2 MHz. Bypass VREG to AGND with a 1 F or greater capacitor. Because the LDO supplies the gate drive current, the output of VREG is subjected to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. The LDO has been optimized to handle these transients without overload faults. Due to the gate drive loading, using the VREG output for other auxiliary system loads is not recommended. The LDO includes a current limit well above the expected maximum gate drive load. This current limit also includes a short-circuit fold back to further limit the VREG current in the event of a short-circuit fault.
INPUT POWER
The ADP1828 is powered from the IN pin from 3.0 V up to 18 V. The internal low dropout linear regulator, regulates the IN voltage down to 5 V when IN is between 5.5 V and 18 V. The output of the LDO is denoted as VREG. The control circuits, gate drivers, and the external boost capacitor operate from the LDO output for IN between 5.5 V and 18 V. PV powers the low-side MOSFET gate drive (DL), and IN powers the internal control circuitry. Bypass PV to PGND with a 1 F or greater capacitor, and bypass IN to GND with a 0.1 F or greater capacitor. Bypass the power input to PGND with a suitably large capacitor. The VREG output is sensed by the undervoltage lock-out (UVLO) circuit to be certain that enough voltage headroom is available to run the controllers and gate drivers. As VREG rises above about 2.7 V, the controllers are enabled. The IN voltage is not directly monitored by the UVLO circuit. If the IN voltage is insufficient to allow VREG to be above the UVLO threshold, the controllers are disabled, but the LDO continues to operate. The LDO is enabled and cannot be turned off whenever EN is high, even if VREG is below the UVLO threshold.
SOFT START
The ADP1828 employs a programmable soft start that reduces input current transients and prevents output overshoot. SS drives an auxiliary positive input to the error amplifier; thus, the voltage at this pin regulates the voltage at the feedback control pin. Program the soft start by connecting a capacitor from SS to GND. On startup, the capacitor charges from an internal 90 k resistor to 0.8 V. The dc-to-dc converter output voltage rises with the voltage at the soft start pin, allowing the output voltage to rise slowly and reducing the inrush current.
Rev. 0 | Page 14 of 32
ADP1828
If the output voltage is precharged prior to turn-on, the ADP1828 prevents reverse inductor current, which would discharge the output capacitor. Once the voltage at SS exceeds the regulation voltage (typically 0.6 V), the reverse current is re-enabled to allow the output voltage regulation to be independent of load current. When a controller is disabled or experiences any form of fault condition, the soft start capacitor is discharged through an internal 6 k resistor, so that at restart or recovery from fault the output voltage soft starts again. the current-limit resistor, the inverting comparator input is similarly forced below PGND and an overcurrent fault is flagged. The normal transient ringing on the switch node is ignored for 100 ns after the synchronous rectifier turns on, so the overcurrent condition must also persist for 100 ns for a fault to be flagged. When the ADP1828 senses an overcurrent condition, the next switching cycle is suppressed, the soft start capacitor is discharged through an internal 6 k resistor, and the error amplifier output voltage is pulled down. The ADP1828 remains in this mode for as long as the overcurrent condition persists. Note that the current-limit scheme in the ADP1828 is not the same as a short-circuit protection. The ADP1828 does not go into current foldback in the event of a short circuit. The shortcircuit output current is the current limit set by the RCL resistor and is monitored cycle by cycle. When the overcurrent condition is removed, operation resumes in soft start mode.
ERROR AMPLIFIER
The ADP1828 error amplifier is an operational amplifier. The ADP1828 senses the output voltage through an external resistor divider at the FB pin. The FB pin is the inverting input to the error amplifier. The error amplifier compares this feedback voltage to the internal 0.6 V reference, and the output of the error amplifier appears at the COMP pin. The COMP pin voltage then directly controls the duty cycle of the switching converter. A series/parallel RC network is tied between the FB pin and the COMP pin to provide the compensation for the buck converter control loop. A detailed design procedure for compensating the system is provided in the Compensating the Voltage Mode Buck Regulator section. The error amplifier output is clamped between a lower limit of about 0.75 V and a higher limit of up to about 3.6 V, depending on the VREG voltage. When the COMP pin is low, the switching duty cycle goes to 0%, and when the COMP pin is high, the switching duty cycle goes to the maximum. The SS and TRK pins are auxiliary positive inputs to the error amplifier. Whichever voltage is lowest (SS, TRK, or the internal 0.6 V reference) controls the FB pin voltage and the output. As a consequence, if two of these inputs are close to each other, a small offset is imposed on the error amplifier.
MOSFET DRIVERS
The DH pin drives the high-side switch MOSFET. This is a boosted 5 V gate driver that is powered by a bootstrap capacitor circuit. This configuration allows the high-side, N-channel MOSFET gate to be driven above the input voltage, allowing full enhancement and a low voltage drop across the MOSFET. The bootstrap capacitor is connected from the SW pin to the BST pin. A bootstrap Schottky diode connected from the PV pin to the BST pin recharges the boost capacitor every time the SW node goes low. Use a bootstrap capacitor value greater than 100x the high-side MOSFET input capacitance. In practice, the switch node can run up to 24 V of input voltage, and the boost nodes can operate more than 5 V above this to allow full gate drive. The IN pin can be run from 3 V to 18 V. The switching cycle is initiated by the internal clock signal. The high-side MOSFET is turned on by the DH driver, and the SW node goes high, pulling up on the inductor. When the internally generated ramp signal crosses the COMP pin voltage, the switch MOSFET is turned off and the low-side synchronous rectifier MOSFET is turned on by the DL driver. Active break-beforemake circuitry as well as a supplemental fixed dead time are used to prevent cross-conduction in the switches. The DL pin provides the gate drive for the low-side MOSFET synchronous rectifier. Internal circuitry monitors the external MOSFETs to ensure break-before-make switching to prevent cross-conduction. An active dead-time reduction circuit reduces the break-before-make time of the switch to limit the losses due to current flowing through the synchronous rectifier body diode.
CURRENT-LIMIT SCHEME
The ADP1828 employs a programmable, cycle-by-cycle lossless current-limit circuit that uses an inexpensive resistor to set the threshold. Every switching cycle, the synchronous rectifier turns on for a minimum time and the voltage drop across the MOSFET RDSON is measured to determine if the current is too high. This measurement is done by an internal current-limit comparator and an external current-limit setting resistor. The resistor is connected between the switch node (that is the drain of the rectifier MOSFET) and the CSL pin. The CSL pin, which is the inverting input of the comparator, forces 50 A through the resistor to create an offset voltage drop across it. When the inductor current is flowing in the MOSFET rectifier, its drain is forced below PGND by the voltage drop across its RDSON. If the RDSON voltage drop exceeds the preset drop on
Rev. 0 | Page 15 of 32
ADP1828
The PV pin provides power to the low-side drivers. It is limited to 5.5 V maximum input and should have a local decoupling capacitor to PGND. The synchronous rectifier is turned on for a minimum time of about 200 ns on every switching cycle in order to sense the current. This minimum off-time plus the nonoverlap dead time puts a limit on the maximum high-side switch duty cycle based on the selected switching frequency. Typically, this maximum duty cycle is about 90% at 300 kHz switching. At 1.2 MHz switching, it reduces to about 70% maximum duty cycle. with fOSC. The 2x output is suitable for synchronizing the dual channel ADP1829 controller (see Table 4). Table 4. CLKOUT Truth Table1
EN H H H L
1
CLKSET L H X X
SYNC H/L H/L Clock in X
CLKOUT 1x fOSC 2x fOSC Clock L
Comment 180 out of phase with fOSC In phase with fOSC CLKOUT in-sync with clock in CLKOUT is low
SETTING THE OUTPUT VOLTAGE
The output voltage is set using a resistive voltage divider from the output to FB. The voltage divider splits the output voltage to the 0.6 V FB regulation voltage to set the regulation output voltage. The output voltage can be set to as low as 0.6 V and as high as 85% of the power input voltage.
X: don't care, H: Logic high, L: Logic low.
SWITCHING FREQUENCY CONTROL AND SYNCHRONIZATION
The ADP1828 has a logic controlled frequency select input, FREQ, which sets the switching frequency to 300 kHz or 600 kHz. Drive FREQ low at 300 kHz and high at 600 kHz. The frequency can also be set to between 300 kHz and 600 kHz by connecting a resistor between FREQ and GND. A 24.9 k sets the frequency to 600 kHz, 35.7 k to 450 kHz, and 57.6 k to 300 kHz. Figure 33 shows fOSC as a function of RFREQ.
600 TA = 25C 550
To synchronize the ADP1828 switching frequency to an external signal, drive the SYNC input with an external clock or with the CLKOUT signal from another ADP1828. The ADP1828 can be synchronized to between 1x and 2x the internal oscillator frequency. If fOSC is set by RFREQ, then the synchronization frequency range is from fOSC up to 600 kHz. Driving SYNC faster than recommended for the FREQ setting results in a small ramp signal, which could affect the signal-tonoise ratio and the modulator gain and stability. When an external clock is detected at the first SYNC edge, the internal oscillator is reset and the clock control shifts to SYNC. The SYNC edges then trigger subsequent clocking of the PWM outputs. The high-side MOSFET turn-on follows the rising edge of the sync input by approximately 320 ns (see Figure 34 for an illustration). If the external SYNC signal disappears during operation, the ADP1828 reverts to its internal oscillator and experiences a delay of no more than a single cycle of the internal oscillator.
OSCILLATOR FREQUENCY (kHz)
500 450 VIN = 3V 400 350 300 VIN = 5V
SYNC
320ns DH
06865-034
250 200 24000
DT
29000
34000
39000
44000
49000
54000
59000
DL
DT (DEAD TIME) = 40ns
06865-035
RFREQ ()
Figure 33. fOSC vs. RFREQ
The SYNC input is used to synchronize the converter switching frequency to an external signal. This allows multiple ADP1828 converters to be operated at the same frequency to prevent frequency beating or other interactions. The ADP1828 has a clock output (CLKOUT), which can be used for synchronizing the ADP1829 and other ADP1828 controllers, thus eliminating the need for an external clock source. Pulling CLKSET low sets the frequency at CLKOUT to 1x the internal oscillator frequency, fOSC, and is 180 out of phase with fOSC. The 1x output is suitable for synchronizing other ADP1828s. Setting CLKSET high (connect to VREG) sets the frequency to 2x fOSC and is in phase
Figure 34. Synchronization
Rev. 0 | Page 16 of 32
ADP1828
COMPENSATION
The control loop is compensated by an external series RC network from COMP to FB and sometimes requires a series RC in parallel with the top voltage divider resistor. COMP is the output of the internal error amplifier. The internal error amplifier compares the voltage at FB to the internal 0.6 V reference voltage. The difference between the FB voltage and the 0.6 V reference voltage is amplified by the openloop voltage 1000 volt-to-volt gain of the error amplifier. To optimize the ADP1828 for stability and transient response for a given set of external components and input/output voltage conditions, choose the compensation components carefully. For more information on choosing the compensation components, see the Compensating the Voltage Mode Buck Regulator section.
THERMAL SHUTDOWN
In most applications, the ADP1828 controller itself does not generate a significant amount of heat under normal conditions, even when driving relatively large MOSFETs. However, the surrounding power components or other circuits on the same PCB could heat up the PCB to an unsafe operating temperature. A thermal shutdown protection circuit on the ADP1828 shuts off the LDO and the controllers if the die temperature exceeds approximately 145C, but this is a gross fault protection only and should not be depended on for system reliability.
SHUTDOWN CONTROL
The ADP1828 dc-to-dc converter features a low power shutdown mode that reduces the quiescent supply current to 20 A, or 40 A when IN is tied to VREG. To shut down the ADP1828, drive EN low. To turn it on, drive EN high or tristate EN. For automatic startup, connect EN to IN.
POWER-GOOD INDICATOR
The ADP1828 features an open-drain power-good output (PGOOD) that sinks current when the output voltage drops 8.3% below or rises 25% above the nominal regulation voltage. Two comparators measure the voltage at FB to set these thresholds. The PGOOD comparator directly monitors FB, and the threshold is fixed at 0.55 V for undervoltage and 0.75 V for overvoltage. The PGOOD output also sinks current if an overtemperature or input undervoltage condition is detected and is operational with power-input voltage as low as 1.0 V. Use this output as a logical power-good signal by connecting a pull-up resistor from PGOOD to an appropriate supply voltage.
TRACKING
The ADP1828 features a tracking input, TRK that makes the output voltage track another voltage, that is, the master voltage. This feature is especially useful in core and I/O voltage sequencing applications where the output of the ADP1828 can be set to track and not exceed another voltage. The internal error amplifier includes three positive inputs--the internal 0.6 V reference voltage, and the SS and TRK pins. The error amplifier regulates the FB pin to the lowest of the three inputs. To track a supply voltage, tie the TRK pin to a resistor divider from the voltage to be tracked. If the TRK function is not used, tie the TRK pin to VREG.
Rev. 0 | Page 17 of 32
ADP1828 APPLICATION INFORMATION
SELECTING THE INPUT CAPACITOR
The input current to a buck converter is a pulse waveform. It is zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor carries the input ripple current, allowing the input power source to supply only the dc current. The input capacitor needs sufficient ripple current rating to handle the input ripple as well as an ESR that is low enough to mitigate input voltage ripple. For the usual current ranges for these converters, it is good practice to use two parallel capacitors placed close to the drains of the highside switch MOSFETs (one bulk capacitor of sufficiently high current rating as calculated in Equation 2 along with a 10 F ceramic capacitor). Select an input bulk capacitor based on its ripple current rating. First, determine the duty cycle of the output with the larger load current:
D= VOUT V IN
Choose the output bulk capacitor to set the desired output voltage ripple. The impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. The impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, including the equivalent series resistance (ESR) and the equivalent series inductance (ESL). The output voltage ripple can be approximated with:
1 VOUT = I L ESR 2 + 8f C SW OUT + (4 f SW ESL) 2
2
(4)
(1)
where: VOUT is the output ripple voltage. IL is the inductor ripple current. ESR is the equivalent series resistance of the output capacitor (or the parallel combination of ESR of all output capacitors). ESL is the equivalent series inductance of the output capacitor (or the parallel combination of ESL of all capacitors). Note that the factors of 8 and 4 in Equation 4 would normally be 2 for sinusoidal waveforms, but the ripple current waveform in this application is triangular. Parallel combinations of different types of capacitors, for example, a large aluminum electrolytic in parallel with MLCCs, may give different results. Usually the impedance is dominated by ESR at the switching frequency, as stated in the maximum ESR rating on the capacitor data sheet, so this equation reduces to VOUT IL ESR (5) Electrolytic capacitors have significant ESL also, on the order of 5 nH to 20 nH, depending on type, size, and geometry, and PCB traces contribute some ESR and ESL as well. However, using the maximum ESR rating from the capacitor data sheet usually provides some margin such that measuring the ESL is not usually required. In the case of output capacitors, the impedance of the ESR and ESL at the switching frequency are small, for instance, where the effective output capacitor is a bank of parallel MLCC capacitors, the capacitive impedance dominates and the ripple equation reduces to
The input capacitor ripple current is approximately
I RIPPLE I L D(1 - D )
(2)
where: IL is the maximum inductor or load current. D is the duty cycle.
OUTPUT LC FILTER
The output LC filter smoothes the switched voltage at SW, making the dc output voltage. Choose the output LC filter to achieve the desired output ripple voltage. Because the output LC filter is part of the regulator negative-feedback control loop, the choice of the output LC filter components affects the regulation control loop stability. Choose an inductor value such that the inductor ripple current is approximately 1/3 of the maximum dc output load current. Using a larger value inductor results in a physical size larger than required and using a smaller value results in increased losses in the inductor and/or MOSFET switches. Choose the inductor value by the following equation:
L=
f SW
V 1 VOUT 1 - OUT V IN x I L
(3)
VOUT
I L 8C OUT f SW
(6)
where: L is the inductor value. fSW is the switching frequency. VOUT is the output voltage. VIN is the input voltage. IL is the inductor ripple current, typically 1/3 of the maximum dc load current.
Make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current.
Rev. 0 | Page 18 of 32
ADP1828
During a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation, due to a change in load, is dependent on the output capacitor characteristics. Again, usually the capacitor ESR dominates this response, and the VOUT in Equation 6 can be used with the load step current value for IL. The conduction losses may need an adjustment to account for the MOSFET RDSON variation with temperature. Note that MOSFET RDSON increases with increasing temperature. The MOSFET data sheet should list the thermal resistance of the package, JA, along with a normalized curve of the temperature coefficient of the RDSON. For the power dissipation estimated in Equation 10, calculate the MOSFET junction temperature rise over the ambient temperature of interest: TJ = TA + JAPD (11) Then, calculate the new RDSON from the temperature coefficient curve and the RDSON specification at 25C. An alternate method to calculate the MOSFET RDSON at a second temperature, TJ, is RDSON @ TJ = RDSON @ 25C (1 + TC(TJ - 25C)) (12) where TC is the temperature coefficient of the MOSFET's RDSON, and its typical value is 0.004/C. Then the conduction losses can be recalculated and the procedure iterated until the junction temperature calculations are relatively consistent. The synchronous rectifier, or low-side MOSFET, carries the inductor current when the high-side MOSFET is off. The lowside MOSFET transition loss is small and can be neglected in the calculation. For high input voltage and low output voltage, the low-side MOSFET carries the current most of the time. Therefore, to achieve high efficiency, it is critical to optimize the low-side MOSFET for low on resistance. In cases where the power loss exceeds the MOSFET rating or lower resistance is required than is available in a single MOSFET, connect multiple low-side MOSFETs in parallel. The equation for low-side MOSFET power loss is V PLS (I LOAD ) 2 R DSON 1 - OUT V IN where: PLS is the total low-side MOSFET power loss. RDSON is the total on resistance of the low-side MOSFET(s). Check the gate charge losses of the synchronous rectifier using Equation 8 to be sure it is reasonable. If multiple low-side MOSFETs are used in parallel, then use the parallel combination of the on resistances for determining RDSON to solve this equation. (13)
SELECTING THE MOSFETS
The choice of MOSFET directly affects the dc-to-dc converter performance. The MOSFET must have low on resistance to reduce I2R losses and low gate charge to reduce transition losses. In addition, the MOSFET must have low thermal resistance to ensure that the power dissipated in the MOSFET does not result in excessive MOSFET die temperature. The high-side MOSFET carries the load current during on-time and usually carries most of the transition losses of the converter. Typically, the lower the MOSFET's on resistance, the higher the gate charge and vice versa. Therefore, it is important to choose a high-side MOSFET that balances the two losses. The conduction loss of the high-side MOSFET is determined by the equation
V PC (I LOAD ) 2 R DSON OUT V IN
(7)
where: PC is the conduction power loss. RDSON is the MOSFET on resistance. The gate charging loss is approximated by the equation
PG V PV Q G f SW
(8)
where: PG is the gate charging loss power. VPV is the gate driver supply voltage. QG is the MOSFET total gate charge. fSW is the converter switching frequency. The high-side MOSFET transition loss is approximated by the equation
PT = V IN I LOAD (t R + t F ) f SW 2
(9)
where: PT is the high-side MOSFET switching loss power. tR is the MOSFET rise time. tF is the MOSFET fall time. The total power dissipation of the high-side MOSFET is the sum of all the previous losses, or
PHS PC + PG + PT
(10)
where PHS is the total high-side MOSFET power loss.
Rev. 0 | Page 19 of 32
ADP1828
SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set through the current-limit resistor, RCL. The current sense pin, CSL, sources 50 A through the external current-limit setting resistor, RCL. This creates an offset voltage of RCL multiplied by the 50 A CSL current. When the drop across the low-side MOSFET RDSON is equal to or greater than this offset voltage, the ADP1828 flags a current-limit event. Because the CSL current and the MOSFET RDSON vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. To do this, use the peak current in the inductor, which is the desired current-limit level plus the ripple current, the maximum RDSON of the MOSFET at its highest expected temperature, and the minimum CSL current:
FB is 100 nA. For a 0.15% degradation in regulation voltage and with 100 nA bias current, the low-side resistor, RBOT, needs to be less than 9 k, which results in 67 A of divider current. For RBOT, use a 1 k to 10 k resistor. A larger value resistor can be used, but results in a reduction in output voltage accuracy due to the input bias current at the FB pin, while lower values cause increased quiescent current consumption. Choose RTOP to set the output voltage by using the following equation:
V - VFB RTOP = R BOT OUT VFB

(15)
where: RTOP is the high-side voltage divider resistance. RBOT is the low-side voltage divider resistance. VOUT is the regulated output voltage. VFB is the feedback regulation threshold, 0.6 V.
RCL =
I LPK R DSON ( MAX ) - 38 mV 42 A
(14)
COMPENSATING THE VOLTAGE MODE BUCK REGULATOR
Assuming the LC filter design is complete, the feedback control system can then be compensated. Good compensation is critical to proper operation of the regulator. Calculate the quantities in Equation 16 through Equation 44 to derive the compensation values. The goal is to guarantee that the voltage gain of the buck converter crosses unity at a slope that provides adequate phase margin for stable operation. Additionally, at frequencies above the crossover frequency (fCO), guaranteeing sufficient gain margin and attenuation of switching noise are important secondary goals. For initial practical designs, a good choice for the crossover frequency is one tenth of the switching frequency, calculate first
f CO = f SW 10 (16)
where: ILPK is the peak inductor current. -38 mV is the CSL threshold voltage. Because the buck converters are usually running a fairly high current, PCB layout and component placement may affect the current-limit setting. An iteration of the RCL value may be required for a particular board layout and MOSFET selection. If alternate MOSFETs are substituted at some point in production, these resistor values may also need an iteration.
ACCURATE CURRENT-LIMIT SENSING
The RDSON of the external low-side MOSFET can vary by more than 50% over the temperature range. Accurate current-limit sensing can be achieved by adding a current sense resistor from the source of the low-side MOSFET to PGND. Make sure that the power rating of the current sense resistor is adequate for the application. Apply Equation 14 to calculate RCL and replace RDSON(MAX) with RSENSE.
VIN
This gives sufficient frequency range to design a compensation scheme that attenuates switching artifacts, while also giving sufficient control loop bandwidth to provide a good transient response. The output LC filter is a resonant network that inflicts two poles upon the response at a frequency (fLC). Next, calculate
ADP1828
DH M1 L VOUT COUT DL CSL RCL RSENSE
06865-037
f LC =
1 2 LC
(17)
M2
Figure 35. Accurate Current-Limit Sensing
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback voltage divider. The output voltage is divided down through the voltage divider and drives the FB feedback input. The regulation threshold at FB is 0.6 V. The maximum input bias current into
Generally speaking, the LC corner frequency is about two orders of magnitude below the switching frequency, and therefore about one order of magnitude below crossover. To achieve sufficient phase margin at crossover to guarantee stability, the design must compensate for the two poles at the LC corner frequency with two zeros to boost the system phase prior to crossover. The two zeros require an additional pole or two above the crossover frequency to guarantee adequate gain margin and attenuation of switching noise at high frequencies.
Rev. 0 | Page 20 of 32
ADP1828
Depending on component selection, one zero might already be generated by the ESR of the output capacitor. Calculate this zero corner frequency, fESR, as
f ESR = 1 2 RESR COUT
Note that if the converter is being synchronized, the ramp voltage, VRAMP, is lower than 1.0 V by the percentage of frequency increase over the nominal setting of the FREQ pin:
(18)
f VRAMP = 1.0 V FREQ f SYNC
(22)
Figure 36 shows a typical Bode plot of the LC filter by itself. The gain of the LC filter at crossover can be linearly approximated from Figure 36 as
AFILTER = ALC + A ESR f A FILTER = -40 dB x log ESR f LC f - 20 dB x log CO f ESR
(19)
For example, if FREQ is grounded or connected to VREG, then fFREQ is 300 kHz or 600 kHz, respectively. If the frequency is set by a resistor, then fFREQ is 300 kHz and fSYNC is the frequency set by the resistor. VRAMP is greater than 1.0 V if fSYNC is less than fFREQ. The rest of the system gain needs to reach 0 dB at crossover. The total gain of the system, therefore, is given by
AT = AMOD + AFILTER + ACOMP
where: AMOD is the gain of the PWM modulator. AFILTER is the gain of the LC filter including the effects of the ESR zero. ACOMP is the gain of the compensated error amplifier.
(23)
If fESR fCO, then add another 3 dB to account for the local difference between the exact solution and the linear approximation in Equation 19.
GAIN
0dB
fLC
fESR
fCO
fSW
FREQUENCY
-40dB/dec
-20dB/dec
AFILTER
PHASE 0
Additionally, the phase of the system must be brought back up to guarantee stability. Note from the Bode plot of the filter that the LC contributes -180 of phase shift (see Figure 36). Because the error amplifier is an integrator at low frequency, it contributes an initial -90. Therefore, before adding compensation or accounting for the ESR zero, the system is already down -270. To avoid loop inversion at crossover, or -180 phase shift, a good initial practical design is to require a phase margin of 60, which is therefore an overall phase loss of -120 from the initial low frequency dc phase. The goal of the compensation is to boost the phase back up from -270 to -120 at crossover. Two common compensation schemes are used, which are sometimes referred to as Type II or Type III compensation, depending on whether the compensation design includes two or three poles (see the Type II Compensator and Type III Compensator sections). Dominant-pole compensation, or single-pole compensation, is referred to as Type I compensation, but it is not very useful for dealing successfully with switching regulators. If the zero produced by the ESR of the output capacitor provides sufficient phase boost at crossover, Type II compensation is adequate. If the phase boost produced by the ESR of the output capacitor is not sufficient, another zero is added to the compensation network, and thus Type III is used. In Figure 37, the location of the ESR zero corner frequency gives a significantly different net phase at the crossover frequency.
-90 FILTER
-180
Figure 36. LC Filter Bode Plot
To compensate the control loop, the gain of the system must be brought back up so that it is 0 dB at the desired crossover frequency. Some gain is provided by the PWM modulation itself.
A MOD V = 20 log IN V RAMP
(20)
For systems using the internal oscillator, this becomes
V A MOD = 20 log IN 1.0 V
(21)
Rev. 0 | Page 21 of 32
06865-038
ADP1828
Use the following guidelines for selecting between Type II and Type III compensators: If f ESRZ If f ESRZ
f CO , use Type II compensation. 2
f > CO , use Type III compensation. 2
PHASE CONTRIBUTION AT CROSSOVER OF VARIOUS ESR ZERO CORNERS GAIN 0dB
Type II Compensator
G (dB)
-1 S LO PE -1 SL O PE
PHASE -180 -270
fZ
fP
CHF
fLC fESR1 fESR2 fESR3 fCO
-40dB/dec
fSW
FREQUENCY
RZ RTOP VOUT RBOT FB EA
CI
COMP
06865-040
-20dB/dec
INTERNAL VREF
Figure 38. Type II Compensation
PHASE 0
If the output capacitor ESR zero frequency is sufficiently low (1/2 of the crossover frequency), use the ESR to stabilize the regulator. In this case, use the circuit shown in Figure 38. Calculate the compensation resistor, RZ, with the following equation:
RZ =
1
RTOP V RAMP f ESR f CO V IN f LC 2
(28)
-90
2
06865-039
where: fCO is chosen to be 1/10 of fSW. VRAMP is 1.0 V. Next, choose the compensation capacitor to set the compensation zero, fZ1, to the lesser of 1/4 of the crossover frequency or 1/2 of the LC resonant frequency
f Z1 = f CO f 1 = SW = 4 40 2R Z C I
-180
3
Figure 37. LC Filter Bode Plot
The following equations are used for the calculation of the compensation components as shown in Figure 38 and Figure 39:
(29)
f Z1 = f Z2 =
f P1
1 2R Z C I 1 2C FF (RTOP + R FF )
(24) (25)
(26)
or
f Z1 = f LC 1 = 2 2 R Z C I
(30)
1 = C I C HF 2R Z C I + C HF
1 2R FF C FF
Solving for CI in Equation 29 yields CI = 20 R Z f SW 1 R Z f LC (31)
Solving for CI in Equation 30 yields (27) CI = (32)
f P2 =
where: fZ1 is the zero produced in the Type II compensation. fZ2 is the zero produced in the Type III compensation. fP1 is the pole produced in the Type II compensation. fP2 in the pole produced in the Type III compensation.
Rev. 0 | Page 22 of 32
ADP1828
Use the larger value of CI from Equation 31 or Equation 32. Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Next, choose the high frequency pole, fP1, to be 1/2 of fSW. f P1 = 1 f SW 2 (33) Next, calculate CI,
CI =
1 2R Z f Z1
(40)
Because of the finite output current drive of the error amplifier, CI needs to be less than 10 nF. If it is larger than 10 nF, choose a larger RTOP and recalculate RZ and CI until CI is less than 10 nF. Since CHF << CI, combining Equation 26 and Equation 36 yields
Since CHF << CI, Equation 26 is simplified to
f P1 =
1 2R Z C HF 1 f SW R Z
(34)
C HF =
1 f SW R Z
(41)
Combine Equation 33 and Equation 34, and solve for CHF,
Next, calculate the feedforward capacitor CFF. Assuming RFF << RTOP, then Equation 25 is simplified to (35) f Z2 = 1 2C FF RTOP 1 2RTOP f Z2 (42)
C HF =
Type III Compensator
G (dB)
Solving CFF in Equation 42 yields
S +1 LO PE
-1 SL O
-1 SL O
PE
C FF =
PE
(43)
-90 PHASE -270
fZ
fP
where fZ2 is obtained from Equation 37 or Equation 38. The feedforward resistor, RFF, can be calculated by combining Equation 27 and Equation 36
CHF RFF RTOP RBOT FB EA COMP CFF RZ CI
R FF =
1 C FF f SW
(44)
VOUT
INTERNAL VREF
Figure 39. Type III Compensation
If the output capacitor ESR zero frequency is greater than 1/2 of the crossover frequency, use the Type III compensator as shown in Figure 39. Set the poles and zeros as follows: f P1 = f P2 =
f Z1 = f Z2 =
Check that the calculated component values are reasonable. For instance, capacitors smaller than about 10 pF should be avoided. In addition, the ADP1828 error amplifier has a finite output current drive, so RZ values less than 3 k and CI values greater than 10 nF should be avoided. If necessary, recalculate the compensation network with a different starting value of RTOP. If RZ is too small or CI is too big, start with a larger value of RTOP. This compensation technique should yield a good working solution. In general, aluminum electrolytic capacitors have high ESR, and Type II compensation is adequate. However, if several aluminum electrolytic capacitors are connected in parallel, and produce a low effective ESR, then Type III compensation is needed. In addition, ceramic capacitors have very low ESR (only a few milliohms) making Type III compensation a better choice. Type III compensation offers better performance than Type II in terms of more low frequency gain and more phase margin and less high frequency gain at the crossover frequency.
1 f SW 2
f CO f 1 = SW = 4 40 2R Z C I
06865-041
(36) (37)
or
f Z1 = f Z2 = f LC 1 = 2 2R Z C I
(38)
Use the lower zero frequency from Equation 37 or Equation 38. Calculate the compensator resistor, RZ
RZ =
RTOP VRAMP f Z1 f CO V IN f LC 2
(39)
Rev. 0 | Page 23 of 32
ADP1828
SOFT START
The ADP1828 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. The soft start is selected by setting the capacitor, CSS, from SS to GND. The ADP1828 charges CSS to 0.8 V through an internal 90 k resistor. The voltage on the soft start capacitor while it is charging is
In most applications, a size 0805 component is sufficient. The use of the RC snubber reduces the overall efficiency, generally by an amount in the range of 0.1% to 0.5%. However, the RC snubber cannot reduce the voltage overshoot. A resistor, shown as RRISE in Figure 40, at the BST pin could help to reduce overshoot and is generally between 1 and 5 .
PV BST RRISE VIN M1 L RCL VOUT
VCSS
t 1 - e 90 k CSS = 0.8 V

(45)
ADP1828
DH SW
The soft start period ends when the voltage on the soft start pin reaches 0.6 V. Substituting 0.6 V for VSS and solving for the soft start time tSS:
t 0.6 V = 0.8 V1 - e 90 k CSS
CSL DL
RSNUB M2 CSNUB COUT
06865-042

(46) (47)
PGND
Figure 40. Application Circuit with a Snubber
t SS = 1.386 RC SS
VOLTAGE TRACKING
The ADP1828 includes a feature that tracks a master voltage. This feature is especially important when multiple ADP1828s (or other controllers such as the ADP1829) are powering separate power supply voltages, such as the core and I/O voltages of a DSP or microcontroller. In these cases, improper sequencing can cause damage to the load. The ADP1828 tracking input is an additional positive input to the error amplifier. The feedback voltage is regulated to the lower of the 0.6 V reference, the SS voltage, or the voltage at TRK, so a lower voltage on TRK limits the output voltage. This feature allows implementation of two different types of tracking: coincident tracking, where the output voltage is the same as the master voltage until the master voltage reaches regulation, or ratiometric tracking, where the output voltage is limited to a fraction of the master voltage. In all tracking configurations, the final value of the master voltage should be higher than the slave voltage. Note that the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. This forces the rise time of the master voltage to be imposed on the slave voltage. If the soft start setting of the slave voltage is longer, the slave comes up more slowly and the tracking relationship is not seen at the output. The slave channel should still have a soft start capacitor to give a small but reasonable soft start time to protect the part in case of restart after a current-limit event.
Because R = 90 k: C SS = t SS x 8 F/ sec
(48)
where tSS is the desired soft start time in seconds.
SWITCHING NOISE AND OVERSHOOT REDUCTION
In any high speed step-down regulator, high frequency noise (generally in the range of 50 MHz to 100 MHz) and voltage overshoot are always present at the gate, the switch node (SW), and the drains of the external MOSFETs. The high frequency noise and overshoot are caused by the parasitic capacitance, Cgd, of the external MOSFET and the parasitic inductance of the gate trace and the packages of the MOSFETs. When the high current is switched, electromagnetic interference (EMI) is generated, which can affect the operation of the surrounding circuits. To reduce voltage ringing at the drain of the MOSFET, an RC snubber can be added between SW and PGND, as illustrated in Figure 40. In most applications, RSNUB is about 2 , and CSNUB about 1.2 nF. RSNUB and CSNUB can be calculated using the following equations:
R SNUB =
1 2fC OSS
(49) (50)
C SNUB = C OSS
where: f is the high frequency ringing measured at the SW node. COSS is the total output capacitance of the top-side and low-side MOSFETs, given in the MOSFET data sheet. The size of the RC snubber components need to be chosen correctly to handle the power dissipation. The power dissipated in RSNUB is:
PSNUB = VIN 2C SNUB f SW
Rev. 0 | Page 24 of 32
ADP1828
VOUT RTOP COMP RBOT FB
VOUT_MASTER
1
EN FOR BOTH ADP1828
TRK ERROR AMPLIFIER 0.6V SS DETAIL VIEW OF RTRKT
MASTER VOLTAGE
VOUT_SLAVE
TRK_SLAVE
06865-043
ADP1828
RTRKB
4
Figure 41. Voltage Tracking
CH1 5.00V CH3 1.00V
BW BW
CH2 1.00V CH4 1.00V
BW
M 100ms
A CH1
2.60V
COINCIDENT TRACKING
The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. Connect the slave TRK input to a resistor divider from the master voltage that is the same as the divider used on the slave FB pin. This forces the slave voltage to be the same as the master voltage. For coincident tracking, use the following equation: RTRKT = RTOP and RTRKB = RBOT where: RTOP and RBOT are the values chosen in the Compensating the Voltage Mode Buck Regulator section. See Figure 42 for an example of a coincident tracking circuit.
POWER COMPONENTS
EN ADP1828 OR ADP1829 SS CSS 1F FB EN
Figure 44. Coincident Tracking of Figure 42
POWER COMPONENTS
3.3V VOUT_MASTER
As the master voltage rises, the slave voltage also rises in the same pattern. Eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the TRK input continues to increase and thus removes itself from influencing the output voltage. To ensure that the output voltage accuracy is not compromised by the TRK pin being too close in voltage to the 0.6 V reference, make sure that the final value of the master voltage is greater than the slave regulation voltage by at least 10%, or 60 mV as seen at the FB node (the higher, the better). A difference of 60 mV between TRK and the 0.6 V reference produces about 3 mV of offset in the error amplifier, or 0.5%, at room temperature, while 100 mV between them produces only 0.6 mV or 0.1% offset. For accurate tracking, set the final voltage at TRK to less than or equal to 0.5 V. However, this condition would trip the PGOOD signal.
ADP1828
RTRKT 20k 1.1V RTRKB 10k CSS 150nF
1.8V VOUT_SLAVE
RATIOMETRIC TRACKING
Ratiometric tracking limits the output voltage to a fraction of the master voltage. For example, the termination voltage for DDR memories (VTT) is set to half the VDDQ voltage.
MASTER VOLTAGE
VOLTAGE
TRK SS FB
RTOP 20k RBOT 10k
06865-044
SLAVE VOLTAGE
TIME
MASTER VOLTAGE
Figure 45. Ratiometric Tracking
SLAVE VOLTAGE
TIME
Figure 43. Coincident Tracking
For ratiometric tracking, the simplest configuration is to tie the TRK pin of the slave channel to the FB pin of the master channel. The advantage of this is having the fewest components, but the accuracy suffers as the TRK pin voltage becomes equal to the internal reference voltage and an offset is imposed on the error amplifier of about -18 mV at room temperature.
VOLTAGE
06865-045
Rev. 0 | Page 25 of 32
06865-047
Figure 42. Example of a Coincident Tracking Circuit
06865-046
ADP1828
A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0.6 V at regulation, for example, 0.5 V. The slave channel can be viewed as having a 0.5 V external reference supplied by the master voltage. Keep in mind that PGOOD is tripped when the TRK voltage is set to less than 0.55 V. Once this is complete, the FB divider for the slave voltage is designed as in the Compensating the Voltage Mode Buck Regulator section except to substitute the 0.5 V reference for the VFB voltage. The ratio of the slave output voltage to the master voltage is a function of the two dividers:
R 1 + TOP R BOT = RTRKT 1 + RTRKB Figure 48 shows an example of DDR memory termination application circuit, where the DDR memory termination voltage, VTT, is 1/2 of VDDQ. VTT can sink current during the off cycle of the ADP1828. The output waveform in Figure 49 shows that VTT changes by one-half of the output change in VDDQ.
POWER COMPONENTS
EN ADP1828 OR ADP1829 SS CSS 1F FB EN
POWER COMPONENTS
2.5V VDDQ
1.25V VTT
ADP1828
RTRKT 40.2k 0.5V RTRKB 10k CSS 150nF
TRK SS FB
RTOP 15k RBOT 10k
06865-050
VOUT V MASTER
(51)
Figure 48. An Example of a DDR Termination Circuit
T TRK
Figure 46 shows an example of ratiometric tracking circuit and Figure 47 shows its voltage tracking waveforms.
POWER COMPONENTS
EN
VDDQ (2.5V 0.25V, AC-COUPLED)
POWER COMPONENTS
EN ADP1828 OR ADP1829 SS CSS 1F FB 3.3V VOUT_MASTER 1.8V VOUT_SLAVE
1
ADP1828
RTRKT 49.9k 0.55V RTRKB 10k CSS 150nF
3
VTT (1.25V 0.125V, AC-COUPLED)
RTOP 22.6k RBOT 10k
06865-048
TRK SS FB
2
Figure 46. An Example of a Ratiometric Tracking Circuit
CH1 500mV CH3 500mV
BW CH2 BW
100mV
BW
M 200s
A CH1
50.0mV
Figure 49. DDR Termination; Output Waveforms of Figure 48
EN FOR BOTH ADP1828
1
VOUT_MASTER
VOUT_SLAVE
In addition, by selecting the resistor values in the divider carefully, Equation 51 shows that the slave voltage output can be made to have a faster ramp rate than that of the master voltage by setting the TRK voltage at the slave larger than 0.6 V and RTRKB greater than RTRKT. Make sure that the master SS period is long enough (that is, use a sufficiently large SS capacitor) such that the input inrush current does not run into the current limit of the power supply during startup.
EN FOR BOTH ADP1828
TRK_SLAVE
4
1
06865-049
CH1 5.00V CH3 1.00V
BW BW
CH2 1.00V CH4 1.00V
BW
M 100ms
A CH1
2.60V
VOUT_MASTER TRK_SLAVE
Figure 47. Ratiometric Tracking of Figure 46
Another option is to add another tap to the divider for the master voltage. Split the RBOT resistor of the master voltage into two pieces, with the new tap at 0.5 V when the master voltage is in regulation. This saves one resistor, but be aware that Type III compensation on the master voltage causes the feedforward signal of the master voltage to appear at the TRK input of the slave channel.
Rev. 0 | Page 26 of 32
VOUT_SLAVE
4
CH1 5.00V CH3 1.00V
BW BW
CH2 1.00V CH4 1.00V
BW
M 100ms
A CH1
2.60V
Figure 50. Ratiometric Tracking of Figure 46 with RTRKT = 5 k
06865-052
06865-051
ADP1828
THERMAL CONSIDERATIONS
The current required to drive the external MOSFETs comprises the vast majority of the power dissipation of the ADP1828. The on-chip LDO regulates down to 5 V, and this 5 V supplies the drivers. The full gate drive current passes through the LDO and is then dissipated in the gate drivers. The power dissipated in the gate drivers on the ADP1828 is power dissipation on the ADP1828 increases. Care must be taken not to exceed the maximum junction temperature. To calculate the junction temperature from the ambient temperature and power dissipation, use the following formula: TJ = TA + PD JA (53)
PD = V IN f SW (Q DH + Q DL )
where: VIN is the voltage applied to IN. fSW is the switching frequency. Q numbers are the total gate charge specifications from the selected MOSFET data sheets.
(52)
The thermal resistance (JA) of the package is 83C/W depending on board layout, and the maximum specified junction temperature is 125C, which means that at maximum ambient temperature of 85C without airflow, the maximum dissipation allowed is about 1 W. A thermal shutdown protection circuit on the ADP1828 shuts off the LDO and the controllers if the die temperature exceeds approximately 145C, but this is a gross fault protection only and should not be depended on for system reliability.
The power dissipation heats up the ADP1828. As the switching frequency, the input voltage, and the MOSFET size increase, the
Rev. 0 | Page 27 of 32
ADP1828 PCB LAYOUT GUIDELINE
In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. While other circuits carry high dc current and can produce significant IR voltage drops. The key to proper PCB layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. When designing PCB layouts, be sure to keep high current loops small. In addition, keep compensation and feedback components away from the switch nodes and their associated components. The following is a list of recommended layout practices for the synchronous buck controller arranged by decreasing order of importance: * The current waveform in the top and bottom FETs is a pulse with very high dI/dt, so the path to, through, and from each individual FET should be as short as possible and the two paths should be commoned as much as possible. In designs that use a pair of D-Pak or a pair of SO-8 FETs on one side of the PCB, it is best to counter-rotate the two so that the switch node is on one side of the pair and the high-side drain can be bypassed to the low-side source with a suitable ceramic bypass capacitor, placed as close as possible to the FETs in order to minimize inductance around this loop through the FETs and capacitor. The recommended bypass ceramic capacitor values range from 1 F to 22 F depending upon the output current. This bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the PGND plane. The negative terminals of GND, IN bypass, and a soft start capacitor (as well as the bottom end of the output feedback divider resistors) should be tied to an almost isolated small AGND plane. All of these connections should attach from their respective pins to the AGND plane that are as short as possible. No high current or high dI/dt signals should be connected to this AGND plane. The AGND area should be connected through one wide trace to the negative terminal of the output filter capacitors. The PGND pin handles a high dI/dt gate drive current returning from the source of the low-side MOSFET. The voltage at this pin also establishes the 0 V reference for the overcurrent limit protection function and the CSL pin. A PGND plane should connect the PGND pin and the PV bypass capacitor, 1 F, through a wide and direct path to the source of the low-side MOSFET. The placement of CIN is critical for controlling ground bounce. The negative terminal of CIN needs to be placed very close to the source of the low-side MOSFET. * * Avoid long traces or large copper areas at the FB and CSL pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. It is best to position any series resistors and capacitors as closely as possible to these pins. Avoid running these traces close and/or parallel to high dI/dt traces. The switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. This node should be wide to keep resistive voltage drop down. But to minimize the generation of capacitively coupled noise, the total area should be small. Place the FETs and inductor close together on a small copper plane in order to minimize series resistance and keep the copper area small. Gate drive traces (DH and DL) handle high dI/dt and tend to produce noise and ringing. They should be as short and direct as possible. If possible, avoid using feedthrough vias in the gate drive traces. If vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. If the overall PCB layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. It is occasionally helpful to place small value resistors (such as 5 or10 ) in between the DH and DL pins and their respective MOSFET gates. These can be populated with 0 resistors if resistance is not needed. Note that the added gate resistance increases the switching rise and fall times as well as switching power loss in the MOSFET. The negative terminal of the output filter capacitors should be tied closely to the source of the low-side FET. Doing this helps to minimize voltage differences between GND and PGND. All traces should be sized according to the current that is handled as well as their sensitivity in the circuit. Standard PCB layout guidelines mainly address the heating effects of a current in a copper conductor. While these are completely valid, they do not fully cover other concerns such as stray inductance or dc voltage drop. Any dc voltage differential in connections between ADP1828 GND and the converter power output ground can cause a significant output voltage error, as it affects converter output voltage according to the ratio with the 600 mV feedback reference. For example, a 6 mV offset between ground on the ADP1828 and the converter power output causes a 1% error in the converter output voltage.
*
*
*
*
*
Rev. 0 | Page 28 of 32
ADP1828
To achieve an accurate output voltage, proper grounding of the AGND and PGND planes is needed. For light to medium loads, connecting the AGND plane to the PGND plane with a trace is adequate in obtaining good output accuracy (see Figure 51). If the PGND plane is large enough and under a light to medium load, the voltage drop across the PGND plane is negligible. However, under a heavy load, such as at 20 A, the voltage drop across the PGND plane could be significant, thus affecting the accuracy of the output. The AGND plane would then have to be routed directly to the negative terminal of the load and the power supply, as illustrated in Figure 52. The power supply GND terminal and the load GND terminal should be placed as close as possible to each other to minimize the voltage drop across these two terminals, thus improving the output accuracy.
VOUT PGND PLANE SMALL AGND TRACE POWER SUPPLY GND TERMINAL
06865-053
VOUT
LOAD
POWER SUPPLY GND TERMINAL POWER SUPPLY GND TERMINAL IS CONNECTED TO PGND PLANE.
LOAD
06865-054
AGND PLANE
PGND PLANE
AGND PLANE
POWER SUPPLY GND TERMINAL IS CONNECTED TO PGND PLANE.
Figure 51. Grounding Technique for a Light to Medium Load
Figure 52. Proper Grounding Technique for a Heavy Load
RECOMMENDED COMPONENT MANUFACTURERS
Table 5.
Vendor AVX Corporation Central Semiconductor Corp. Coilcraft, Inc. Diodes, Inc. International Rectifier Murata Manufacturing Co., Ltd. ON Semiconductor Rubycon Corporation Sanyo Sumida Corporation Taiyo Yuden, Inc. Toko America, Inc. United Chemi-Con, Inc. Vishay Siliconix Wurth Elektronic Components Capacitors Diodes Inductors Diodes Diodes, MOSFETs Capacitors, inductors Diodes, MOSFETs Capacitors Capacitors Inductors Capacitors, inductors Inductors Capacitors Diodes, MOSFETs, resistors, capacitors Inductors
Rev. 0 | Page 29 of 32
ADP1828 APPLICATION CIRCUITS
VIN = 3.3V C5 1F D1 VREG IN R6 100k C6 1F EN FREQ SYNC PGOOD COMP C2 68pF R8 8.06k CSS 100nF SS GND AGND PV TRK BST DH SW CSL DL PGND FB CLKOUT CLKSET AGND PGND C4 0.22F R4 3k M1B CIN 22F 6.3V x3 M1A L1 = 1.0H COUT1 100F 6.3V COUT2 47F 6.3V R1 10k R2 10k
ADP1828
OUTPUT 1.2V, 5A R3 210 C1 1.8nF
C3 3.3nF
CIN: CERAMIC, 22F/6.3V/X5R/0805 COUT1: CERAMIC, 100F/6.3V/X5R/1210 COUT2: CERAMIC, 47F/6.3V/X5R/1206
Figure 53. Application Circuit for VIN = 3.3 V, All Ceramic Solution
VIN = 10V TO 13V
C7 1F VREG IN R6 100k C6 1F EN FREQ SYNC PGOOD COMP C2 120pF R8 6.04k CSS 100nF SS PV
C5 1F D1 TRK BST DH SW CSL DL PGND FB CLKOUT CLKSET GND AGND C4 0.22F R4 2.8k M1B
CIN 22F 16V
ADP1828
M1A L1 = 1.8H COUT 100F 6.3V
OUTPUT 3.3V, 4A R3 412 R1 20k R2 4.42k C1 1.0nF
AGND PGND
C3 4.7nF
CIN: CERAMIC, 22F/6.3V/X5R/1210 COUT: CERAMIC, 100F/6.3V/X5R/1210
Figure 54. Application Circuit for VIN = 12 V, All Ceramic Solution
Rev. 0 | Page 30 of 32
06865-056
fSW = 600kHz
L1: TOKO, FDV0630-1R8M D1: VISHAY, BAT54 M1A, M1B: VISHAY, DUAL-FET Si7958DP
06865-055
fSW = 600kHz
L1: TOKO, FDV0630-1R0M D1: BAT54 M1A, M1B: VISHAY, DUAL-FET Si7940DP
ADP1828
VBIAS = 5V C5 1F D1 VREG IN R6 100k C6 1F EN FREQ SYNC PGOOD COMP C2 220pF R8 4.99k CSS 100nF SS GND AGND PV TRK BST DH SW CSL DL PGND FB CLKOUT CLKSET AGND PGND C4 0.47F R4 3.3k M2 VIN = 2.5V TO 8V CIN 270F 16V x2 M1 L1 = 1H COUT1 10F 6.3V COUT2 820F 2.5V x2
ADP1828
OUTPUT 1.0V, 15A R3 210 R1 10k R2 15k C1 1.8nF
C3 4.7nF
fSW = 300kHz
Figure 55. Application Circuit for VIN = 2.5 V to 8 V
VIN = 10V TO 18V CIN 180F 20V x3 D1 VREG IN R6 100k C6 1F EN FREQ SYNC PGOOD COMP C2 47pF R8 26.1k CSS 200nF SS GND AGND PV TRK BST DH SW CSL DL PGND FB CLKOUT CLKSET AGND PGND C4 0.47F R4 2.2k M2 x 2 COUT2 1000F x3
C5 1F
C7 1F
M1 x 2 L1 = 0.47H COUT1 47F 6.3V R1 20k R2 10k OUTPUT 1.8V, 27A R3 6.49k C1 680nF
ADP1828
C3 2.7nF
Figure 56. Application Circuit with 27 A Output
Rev. 0 | Page 31 of 32
06865-058
CIN: SANYO, OSCON 20SP180M COUT2: SANYO, POSCAP 2R5TPD1000M5 L1: WURTH ELEKTRONIC, 0.47H, 744355147
fSW = 300kHz
D1: VISHAY, BAT54 M1: INFINEON, 2 x BSC080N03LS M2: INFINEON, 2 x BSC030N03LS
06865-057
CIN: SANYO, OSCON 16SP270M COUT2: SANYO, OSCON 2R5SEPC820M L1: COILTRONICS, HC7-1R0
M1: INFINEON BSC080N03LS M2: INFINEON BSC030N03LS D1: VISHAY, BAT54
ADP1828 OUTLINE DIMENSIONS
0.345 0.341 0.337
20
11
0.158 0.154 0.150
1 10
0.244 0.236 0.228
PIN 1
0.065 0.049
0.069 0.053
0.010 0.004 COPLANARITY 0.004
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
8 0
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AD
Figure 57. 20-Lead Shrink Small Outline Package [QSOP] 150 mil Body (RQ-20) Dimensions shown in inches
ORDERING GUIDE
Model ADP1828YRQZ-R72 ADP1828LC-EVALZ2 ADP1828HC-EVALZ2
1 2
Temperature Range1 -40C to +85C
Package Description 20-Lead Shrink Small Outline Package (QSOP) Evaluation Board with 5 A Output Evaluation Board with 20 A Output
Package Option RQ-20
Quantity 1,000 1 1
Operating Junction Temperature is -40C to +125C. Z = RoHS Compliant Part.
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06865-0-9/07(0)
Rev. 0 | Page 32 of 32

▲Up To Search▲

Price & Availability of ADP1828LC-EVALZ

	To Download ADP1828LC-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .